1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device.
2. Description of the Related Art
As the integration of the semiconductor devices in integrated circuits is increased more and more, the dimensions thereof, such as pattern and line-width, is reduces to less and less. However, the reduced line-width of the semiconductor devices results in the increased resistance of the wiring line between polysilicon electrode and devices and therefore, the RC delay is increased. In this circumstance, the operation rate of the semiconductor devices is adversely affected. Since the resistance of the silicide is lower than that of polysilicon and the thermal stability thereof is higher than that of common material for interconnect, such as aluminum, a salicide is formed at the interface between the gate electrode and the drain/source region and between the interconnects for reducing the sheet resistance of the drain/source region and completing the shallow junction between the metal and metal oxide semiconductor (MOS). In the conventional manufacture process, at least one metal layer is formed on silicon substrate and then, conducted a thermal process to convert the metal layer into a salicide. Alternatively, the salicide is directly covered on the substrate. The former is commonly used in the current manufacture of semiconductor devices. FIGS. 1A to 1C are schematic, cross-sectional view illustrating of fabrication of self-aligned silicide according to the conventional method.
Referring to FIG. 1A, a gate electrode including a patterned gate oxide layer 102 and polysilicon layer 104 is provided on a semiconductor substrate 100. A spacer 106 is formed at the sidewall of the gate electrode and drain/source 108 is formed adjacent to the gate electrode. A titanium layer 110 is sputtered on the substrate by DC Magnetron Sputtering process to cover the gate electrode, space 106 and source/drain 108. Then, a titanium nitride layer 112 is formed on titanium layer 110 as passivation layer.
Referring to FIG. 1B, the substrate with metal layer 110 and passivation layer 112 is conducted a rapid thermal process at a temperature of 600.degree. C. to 650.degree. C. In this condition, the portion of the metal layer 110 which contacts with the silicon, such as the polysilicon layer 104 and source/drain 108, is reacted with the silicon in polysilicon layer 104, source/drain 108 to form a salicide 114 of C-49 TiSi.sub.2 and the portion of the metal layer 110 which does not contact with the silicon will not convert into salicide. This process is named self-aligned fabrication of salicide.
The passivation layer 112 and remaining metal layer 110 are removed in sequence, as shown in FIG. 1C. The substrate 100 with salicide 114 is treated a second rapid thermal process at a temperature of 700.degree. C. to 750.degree. C. Under this condition, the C-49 type titanium silicide in salicide 114 formed on the surface of the polysilicon 114 and source/drain 108 converts into C-54 type titanium silicide to complete the fabrication of the salicide, wherein the impedance of the former is higher than that of the latter.
However, since the geometry and linewidth effects of the gate electrode, the formation of the salicide on the gate electrode is limited. The thickness of the salicide on the polysilicon layer of gate electrode is thinner that that of the source/drain due to the different rate of the formation thereof. Therefore, the salicide formed on the substrate is un-uniform and thus, affects the contact resistance of the interconnects and the performance of the gate electrode.
In conventional, an approach is to use higher operative temperature and longer reaction time for thermal process to improve the uniformity of the salicide on the polysilicon layer of the gate electrode. However, this thermal process results in the diffusion of the silicon from the source/drain 108 and polysilicon layer 104 of the substrate 100 to the surface of spacer 106. Thus, a lateral growth issue of salicide occurs on the surface of spacer 106, which results in undesired short, bridging and leakage between the gate electrode and source/drain. To avoid the lateral growth issue occurs, an approach using lower operative temperature for thermal process is proposed. However, the thickness and the quality of the salicide formed in this process is unsatisfied.
Therefore, there is a need to provide a process of fabricating self-aligned silicide with uniformity of thickness without electrical short, bridging and leakage occurring between the gate electrode and source/drain.